View TDA7430TR_4309209.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TDA7430 TDA7431
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLER
1
FEATURES
1 STEREO (4STEREO) INPUT + 1 MIXER INPUT INPUT ATTENUATION CONTROL IN 0.5dB STEP VOICE CANCELLER IS AVAILABLE TREBLE MIDDLE AND BASS CONTROL THREE SURROUND MODES ARE AVAILABLE - MUSIC: 4 SELECTABLE RESPONSES - MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES
Figure 1. Package
SDIP42
TQFP44

Table 1. Order Codes
Part Number TDA7431S TDA7430 TDA7430TR Package SDIP42 TQFP44 Tape & Reel
2 SPEAKERS AND 2 RECORD ATTENUATORS: - 2 INDEPENDENT SPEAKERS AND 2 INDEPENDENT RECORD CONTROL IN 1dB STEP FOR BALANCE FACILITY - AVAILABILITY OF LOUDSPEAKER EQUALIZATION FIXED BY EXTERNAL COMPONENTS - INDEPENDENT MUTE FUNCTION
2
DESCRIPTION
The TDA7430/TDA7431 is volume tone (bass middle and treble) balance (Left/Right) processors voice canceller for quality audio applications in car radio and Hi-Fi systems. They reproduce surround sound by using programmable phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS
Figure 2. Pin Connection (TDA7430)
R_IN4 R_IN3 R_IN2 35 CREF PS1 PS2 PS3 LP VS LPVC 34 33 32 31 30 29 28 27 26 25 24 23 12 BASS_RO 13 BASS_RI 14 MIDDLE_LO 15 MIDDLE_LI 16 MIDDLE_RO 17 MIDDLE_RI 18 TREBLE_R 19 TREBLE_L 20 AGND 21 SDA 22 SCL R_IN1 MIX L_IN1 L_IN2 L_IN3 L_IN4 RECOUT_L RECOUT_R L_OUT R_OUT DIG_GND
D95AU220B
PS4 40
44 LP1 HP1 HP2. REAROUT REARIN VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI 1 2 3 4 5 6 7 8 9 10 11
43
42
41
39
38
37
36
June 2004
REV. 10 1/23
TDA7430 - TDA7431
Figure 3. Pin Connection (TDA7431)
PS4 PS3 PS2 PS1 LP LP1 HP1 HP2 VOUTREF VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI BASS_RO BASS_RI MIDDLE_LO MIDDLE_LI MIDDLE_RO MIDDLE_RI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
D95AU219B
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VS CREF NBRO NBRIN LPVC R_IN MIX L_IN NBLIN NBLO RECOUT_L RECOUT_R L_OUT R_OUT DIG_GND SCL SDA ADDR AGND TREBLE_L TREBLE_R
Table 2. Absolute Maximum Ratings
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 11 0 to 70 -55 to 150 Unit V C C
Table 3. Quick Reference Data
Symbol VS VCL THD S/N SC Supply Voltage Max Input Signal Handling Total Harmonic Distortion V = 0.1Vrms f = 1KHz Signal to Noise Ratio Vout = 1Vrms (mode = OFF) Channel Separation f = 1KHz Treble Control (2dB step) Middle Control (2dB step) Bass Control (2dB step) Balance Control 1dB step (LCH, RCH) Mute Attenuation -14 -14 -14 -79 100 Parameter Min. 7 2 0.01 106 90 14 14 14 0 0.1 Typ. 9 Max. 10.2 Unit V VRMS % dB dB dB dB dB dB dB
Table 4. Thermal Data
Symbol Rth j-pin Parameter Thermal Resistance Junction-pins Value 85 Unit C/W
2/23
TDA7430 - TDA7431
Figure 4. TEST CIRCUIT (TDA7430)
2.2F 2.2F 2.2F 0.47F BASSO-R 22nF PS4 9 40 VAR-R 8 BASSO-L 7 VAR-L 6 REAROUT 4 REARIN 5 R-IN4 37 0.47F R-IN3 36 0.47F R-IN2 35 32 MIX 1F
22nF
PS3
41
33
R-IN1
0.47F
4.7nF
PS2
42
31
L-IN1
0.47F
100nF
PS1
43
30
L-IN2
0.47F
1.2nF
LP
44
29
L-IN3
0.47F
5.6nF
LP1
1
28 39
L-IN4 VS
0.47F
5.6nF
TREBLE-R
18
5.6nF
TDA7430
38
10F 22F
100nF
TREBLE-L
19
CREF
100nF
LPVC
34 10 14 11
220nF 100nF BASS-LO 100nF BASS-LI 100nF
22nF
MIDDLE-LO
18nF MIDDLE-LI 22nF MIDDLE-RO 16 15
2.7K
5.6K
12
BASS-RO
18nF
100nF 17 27 RECOUT-L 26 RECOUT-R 25 L-OUT 24 R-OUT 23 DIG-GND 22 SCL 21 SDA 20 AGND HP2 3 HP1 680nF 2 13 BASS-RI
2.7K
MIDDLE-RI
5.6K
D95AU225B
Figure 5. TEST CIRCUIT (TDA7431)
2.2F 2.2F 680nF 0.47F 22nF BASSO-R PS4 1 13 VAR-R 12 BASSO-L 11 VAR-L 10 HP2 8 HP1 7 R-IN 37 1F MIX 36 0.47F L-IN 35 42 VS 10F 2 41 CREF 22F 100nF
22nF
PS3
4.7nF
PS2
3
100nF
PS1
4
40
NBRO 15K
220nF
1.2nF
LP
220nF
5
39
5.6nF
NBRIN
LP1
7.5K 220nF
6
5.6nF
TREBLE-R
22
TDA7431
34
NBLIN 15K
5.6nF
TREBLE-L
220nF
23
33
100nF
NBLO 100nF
LPVC
7.5K
38 14 18 15 BASS-LO
22nF
MIDDLE-LO
18nF MIDDLE-LI 22nF MIDDLE-RO 20 19
100nF BASS-LI 100nF
2.7K
5.6K
16
BASS-RO
18nF
100nF 21 9 VOUTREF 32 RECOUT-L 31 RECOUT-R 30 L-OUT 29 R-OUT 28 DIG-GND 27 SCL 26 SDA 25 ADDR 17 24 BASS-RI
2.7K
MIDDLE-RI
5.6K
D95AU224B
AGND
3/23
MIDDLE-LI
LP1 PS1 43 RPS1 FIX RPS2 RPS3 RPS4 RM RB 30K 42 41 40 19 15 10 7 6 14 11 PS2
HP1
HP2
PS3
PS4
TREBLE-L BASS-LI BASS-LO BASSO-L VAR-L
0.47F
31
1 31.5dB control
2
3
L-IN1
50K
0.47F
30 PS1 90Hz OFF SURR REC ATT 79dB CONTROL PS2 4KHz PS3 400Hz PS4 400Hz
RLP1 RHP1 27 RECOUT-L
Figure 6. Block Diagram (TDA7430)
L-IN2
50K
0.47F
29
MIDDLE-LO
28 SIM MUSIC 3BAND + MOVIE/ MUSIC OFF MOVIE/SIM MIXING AMP TREBLE MIDDLE BASS
-
REAR
L-IN4
+
MUTE
FIX
50K + L-R
+
0.47F
33
I2C BUS DECODER + LATCHES
R-IN1
50K LPF 9KHz SURR 3BAND OFF REAR SURR 50K 44 LP REARIN 4 5 18 TREBLE-R 17 RM 16 13 RB 12 MUTE 79dB CONTROL BASSO-R BASS-RI 9 8 VAR-R
D95AU221B
0.47F EFFECT CONTROL MIXING AMP TREBLE MIDDLE
+ BASS FIX FIX VAR + MUTE REC ATT 79dB CONTROL SPKR ATT
35
R-IN2
50K
-
0.47F
36
R-IN3
50K
0.47F
LPF
+
VOICE ON
37 Vref
R-IN4 SUPPLY
50K
31.5dB control
100K
30K
34 39 AGND CREF VS REAROUT 22F 2.2F 1.2nF 20 38
32
LPVC
MIX
MIDDLE-RI
MIX-IN
5.6nF
18nF 2.7K
22nF
MIDDLE-RO
100nF 5.6K
100nF
THE SWITCHES POSITION MATCHES THE RESET CONDITION
BASS-RO
100nF
1F
2.2F
+
0.47F SURR
VAR
-
4/23
100nF 2.2F 4.7nF 22nF 22nF 5.6nF 100nF 2.7K 18nF 5.6K 22nF 100nF 79dB CONTROL SPKR ATT MUTE 25 L-OUT 22 21 23 SCL SDA DIG GND 24 R-OUT 26 RECOUT-R
TDA7430 - TDA7431
5.6nF
680nF
L-IN3
R5
50K
R6
5.6nF 100nF 22nF NB-LB NBLO 2.2F VAR-L NBLIN NB2 34 30K MIDDLE-LI MIDDLE-LO 4.7nF 22nF
680nF
5.6nF 100nF NB1 NB-LA
2.7K 18nF
5.6K 22nF 100nF
LP1 PS1 4 19 RM FIX RB 18 15 RPS1 RPS3 RPS4 RPS2 3 2 1 23 14 11 10 33 PS2 PS3 PS4
HP1
HP2 TREBLE-L BASS-LI BASS-LO BASSO-L
0.47F
31.5dB control
6
7
8
35
L-in
50K PS1 90Hz OFF 79dB CONTROL SURR REC ATT VAR REAR MUTE FIX MIXING AMP TREBLE MIDDLE BASS 3BAND PS2 4KHz PS3 400Hz PS4 400Hz
RLP1 RHP1 32 RECOUT-L
Figure 7. Block Diagram (TDA7431)
R5
79dB CONTROL FIX VAR + 30K 13 12 39 VAR-R 2.2F NB-RA NBRIN NB-RB NB4 NBRO + MUTE SPKR ATT MUTE 79dB CONTROL 40 NB3 SPKR ATT
R6 SURR SIM MUSIC
-
30
+
-
L-OUT
+ MOVIE/ MUSIC OFF MOVIE/SIM
-
L-R
+
+ I2C BUS DECODER + LATCHES
27 26 28 25
SCL SDA DIG GND ADDR
+ LPF 9KHz SURR 3BAND OFF REAR Vref SURR MUTE 5 LP VS VOUTREF 22F 5.6nF AGND CREF 1.2nF TREBLE-R 42 24 41 9 22 21 RM 20 17 RB 16 79dB CONTROL BASSO-R BASS-RI EFFECT CONTROL MIXING AMP TREBLE MIDDLE BASS FIX
-
29
R-OUT
0.47F
37
LPF
+
VOICE ON
REC ATT
R-in SUPPLY
31
RECOUT-R
50K
31.5dB control
100K
38
36
LPVC
MIX
D95AU222C
MIDDLE-RI
MIX-IN
18nF 2.7K
22nF
MIDDLE-RO
100nF 5.6K
100nF
TDA7430 - TDA7431
THE SWITCHES POSITION MATCHES THE RESET CONDITION
BASS-RO
100nF
1F
5/23
TDA7430 - TDA7431
Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, Vin = 1Vrms; RG = 600, all controls flat (G = 0dB), Effect CTRL = -6dB, MODE = OFF; f = 1KHz unless otherwise specified).
Symbol SUPPLY VS IS SVR Supply Voltage Supply Current Ripple Rejection LCH / RCH out, Mode = OFF 7 10 60 9 18 80 10.2 26 V mA dB Parameter Test Condition Min. Typ. Max. Unit
INPUT STAGE RIN VCL CRANGE AVMIN AVMAX ASTEP VDC AVO1 AVO2 AVO3 RLPV RMIX Input Resistance Clipping Level Control Range Min. Attenuation Max. Attenuation Step Resolution DC Steps Voice Canceler Output 1 Voice Canceler Output 2 Voice Canceler Output 3 Low Pass Filter Resistance Input Impedance adjacent att. step LIN = RIN, RIN = ON, Vmix = 0V FIX, 0dB attenuation LIN = RIN = 0V, Vmix = 1Vrms FIX, 0dB attenuation LIN = RIN, Vmix = 0V FIX, 0dB attenuation -3 5 -1 5 22.4 70 -1 31 THD = 0.3% 35 2 50 2.5 31.5 0 31.5 0.5 0 6 0 6 32 100 1 32 1 3 7 1 7 41.6 130 65 K Vrms dB dB dB dB mV dB dB dB K K
BASS CONTROL Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut 11.5 1 32 14.0 2 44 16.0 3 56 dB dB K
MIDDLE CONTROL Gm MSTEP RM Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut 11.5 1 17.5 14.0 2 25 16.0 3 32.5 dB dB K
TREBLE CONTROL Gt TSTEP Control Range Step Resolution Max. Boost/cut 13.0 1 14.0 2 15.0 3 dB dB
6/23
TDA7430 - TDA7431
Table 5. Electrical Characteristcs (continued)
Symbol EFFECT CONTROL CRANGE SSTEP Control Range Step Resolution 13.0 0.5 1 6 1.5 dB dB Parameter Test Condition Min. Typ. Max. Unit
SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1 GOFF DGOFF GMOV In-phase Gain (OFF) LR In-phase Gain Difference (OFF) In-phase Gain (Movie) Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin Rout , Lin Lout Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin Rout , Lin Lout Movie mode, Effect Ctrl = -6dB 1kHz, 1.4 Vp-p, Rin Rout , Lin Lout Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) , (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) , (Lin Lout) Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin Rout Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin Rout Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Rout 7 42 7 -1 -1 0 0 8 1 1 dB dB dB
DGMOV
LR In-phase Gain Difference (Movie) In-phase Gain (Music)
0
dB
GMUS
7
dB
DGMUS
LR In-phase Gain Difference (Music) Simulated L Output 1
0
dB
LMON1
4.5
dB
LMON2
Simulated L Output 2
-4.0
dB
LMON3
Simulated L Output 3
7.0
dB
RMON1
Simulated R Output 1
- 4.5
dB
RMON2
Simulated R Output 2
3.8
dB
RMON3
Simulated R Output 3
- 20
dB
RLP1 RHPI RLPF
Low Pass Filter Resistance High Pass Filter Resistance LP Pin Impedance
10 60 10
13 78 13
K K K
7/23
TDA7430 - TDA7431
Table 5. Electrical Characteristcs (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SURROUBND SOUBND MATRIX PHASE RPS10 RPS11 RPS12 RPS13 RPS20 RPS21 RPS22 RPS23 RPS30 RPS31 RPS32 RPS33 RPS40 RPS41 RPS42 RPS43 Phase Shifter 1: D1 = 0, D0 = 0 Phase Shifter 1: D1 = 0, D0 = 1 Phase Shifter 1: D1 = 1, D0 = 0 Phase Shifter 1: D1 = 1, D0 = 1 Phase Shifter 2: D3 = 0, D2 = 0 Phase Shifter 2: D3 = 0, D2 = 1 Phase Shifter 2: D3 = 1, D2 = 0 Phase Shifter 2: D3 = 1, D2 = 1 Phase Shifter 3: D5 = 0, D4 = 0 Phase Shifter 3: D5 = 0, D4 = 1 Phase Shifter 3: D5 = 1, D4 = 0 Phase Shifter 3: D5 = 1, D4 = 1 Phase Shifter 4: D7 = 0, D6 = 0 Phase Shifter 4: D7 = 0, D6 = 1 Phase Shifter 4: D7 = 1, D6 = 0 Phase Shifter 4: D7 = 1, D6 = 1 8.3 10 12.6 26.4 4 4.8 6 12.9 8.5 10.2 12.7 27.4 8.5 10.2 12.7 27.4 11.8 14.1 17.9 37.3 5.6 6.8 8.4 18.3 12.1 14.5 18.1 39.1 12.1 14.5 18.1 39.1 15.2 18.3 23.3 48.85 7.2 8.7 10.9 23.7 15.6 18.7 23.3 50.75 15.6 18.7 23.3 50.75 K K K K K K K K K K K K K K K K
SPEAKER & RECORD ATTENUATORS CRANGE SSTEP EA Control Range Step Resolution Attenuation set error Av = 0 to -20dB Av = -20 to -79dB VDC AMUTE RVEA DC Steps Output Mute Condition Input Impedance adjacent att. steps -0.5 -1.5 -3 -3 +70 21 79 1 0 0 0 100 30 39 1.5 1.5 2 3 dB dB dB dB mV dB K
AUDIO OUTPUTS NO(OFF) NO(MOV) NO(Mus) Output Noise (OFF) Output Noise (Movie) Output Noise (Music) Output Mute, Flat BW = 20Hz to 20KHz Mode = Movie BW = 20Hz to 20KHz Mode = Music BW = 20Hz to 20KHz Mode Simulated BW = 20Hz to 20KHz 4 5 30 30 30 Vrms Vrms Vrms Vrms Vrms
NO(MON) Output Noise (Simulated)
8/23
TDA7430 - TDA7431
Table 5. Electrical Characteristcs (continued)
Symbol d SC VOCL ROUT VOUT Distorsion Channel Separation Clipping Level Output Resistance DC Voltage Level d = 0.3% Parameter Test Condition Av = 0 ; Vin = 1Vrms 70 2 10 Min. Typ. 0.01 90 2.5 40 3.8 70 Max. 0.1 Unit % dB Vrms V
BUS INPUTS VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 +5 0.4 1 V V mA V
3
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7430/TDA7431 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in fig.9 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 10). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking.
9/23
TDA7430 - TDA7431
Figure 8. Data validity on the I2C bus
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 9. Timing Diagram of I2C bus
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 10. Acknowledge on the I2C bus
SCL
1
2
3
7
8
9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
4
SOFTWARE SPECIFICATION
4.1 Interface Protocol The interface protocol comprises:

A start condition (S) A chip address byte, containing the TDA7430/TDA7431 address A subaddress bytes A sequence of data (N byte + achnowledge) A stop condition (P)
Figure 11.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D95AU226A
10/23
TDA7430 - TDA7431
5
EXAMPLES
5.1 No Incremental Bus The TDA7430/TDA7431 receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition. Figure 12.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 0 X X SUBADDRESS LSB X D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D95AU306
5.2 Incremental Bus The TDA7430/TDA7431 receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. Figure 13.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 1 X X SUBADDRESS LSB X D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D95AU307
6
DATA BYTES
Address = 80(HEX) ADDR open; 82 (HEX): need to connect supply 6.1 Function Selection Table 6. The first byte (Subaddress)
MSB D7 B B B B B B B B B B D6 X X X X X X X X X X D5 X X X X X X X X X X D4 X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 0 1 INPUT ATTENUATION SURROUND & OUT & EFFECT CONTROL PHASE RESISTOR BASS & NATURAL BASE MIDDLE & TREBLE SPEAKER ATTENUATION "L" SPEAKER ATTENUATION "R" AUX ATTENUATION "L" AUX ATTENUATION"R" INPUT MULTIPLEXER, & AUX OUT SUBADDRESS
B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1
11/23
TDA7430 - TDA7431
Table 7. INPUT ATTENUATION SELECTION
MSB D7 X X X X X X X X D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 INPUT ATTENUATION 0.5 dB STEPS 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 4 dB STEPS X X X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -4 -8 -12 -16 -20 -24 -28
INPUT ATTENUATION = 0 ~ -31.5dB
Table 8.
D7 X X D6 0 1 D5 D4 D3 D2 D1 D0 REAR SWITCH REARIN, REAROUT PIN ACTIVE NO REARIN, REAROUT PIN
12/23
TDA7430 - TDA7431
Table 9. SURROUND SELECTION
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 LSB D0 0 1 0 1 SURROUND MODE SIMULATED MUSIC OFF MOVIE OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21
0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 10. PHASE RESISTOR SELECTION
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 LSB D0 0 1 0 1 SURROUND PHASE RESISTOR PHASE SHIFT 1 (K) 12 14 18 37 PHASE SHIFT 2 (K) 6 7 8 18 PHASE SHIFT 3 (K) 12 14 18 39 PHASE SHIFT 4 (K) 12 14 18 39
0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 1 0 1
13/23
TDA7430 - TDA7431
Table 11. BASS SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 NATURAL BASE NBRIN, NBRO, NBLIN, NBLO PIN ACTIVE NO NBRIN, NBRO, NBLIN, NBLO PIN
0 1
Table 12. SPEAKER/AUX ATT. R & L SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER/AUX ATT 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE
0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 1
0 0 1 1 0 0 1 1 0 0 1 X
0 1 0 1 0 1 0 1 0 1 X X
X = INDIFFERENT 0,1 SPEAKER/AUX ATTENUATION = 0dB ~ -79dB
14/23
TDA7430 - TDA7431
Table 13. MIDDLE & TREBLE SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 MIDDLE 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 TREBLE 2 dB STEPS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
15/23
TDA7430 - TDA7431
Table 14. VOICE CANCELLER/INPUT/RECOUT L & R SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 D1 1 0 0 1 0 1 LSB D0 0 1 VOICE CANCELER OFF ON INPUT MULTIPLEXER IN2 IN3 IN4 IN1 REC OUT "L" VER 1 (3BAND) VER 2 (SURR) VER 3 (REAR) FIX REC OUT "R" VER 1 (3BAND) VER 2 (SURR) VER 3 (REAR) FIX
Table 15.
POWER ON RESET BASS & MIDDLE TREBLE SURROUND & OUT CONTROL+ EFFECT CONTROL SPEAKER/AUX ATTENUATION L &R INPUT ATTENUATION + REAR SWITCH NATURAL BASE INPUT 2dB 0dB OFF + FIX + MAX ATTENUATION MUTE MAX ATTENUATION + ON OFF IN1
Figure 14. PINS: L-OUT, R-OUT, RECOUT-L, RECOUT-R,
Figure 15. PIN: HP1
LP1
VS 20A 100
VS 10K
60K GND
D94AU198
GND
D94AU204
HP2
16/23
TDA7430 - TDA7431
Figure 16. PIN: HP2 Figure 19. PIN: LP1
VS 20A 5.5K 60K
VS 20A
10K HP1 GND
D94AU199
5.5K
GND HP1
D94AU211
Figure 17. PIN: VAR-L, VAR-R,
Figure 20. PIN: CREF
VS 20A
VS 20K 42K 20A
SW
30K GND Vref
D95AU227
20K
D95AU336
GND
Figure 18. PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4,
Figure 21. PIN: SCL, SDA
VS 20A 20A
50K GND GND VREF
D94AU200 D94AU205
17/23
TDA7430 - TDA7431
Figure 22. PIN: PS1, PS2, PS3, PS4, LP Figure 25. PIN: MIX
VS 20A
VS 20A
100K GND
D95AU308
GND
Vref
D94AU123
Figure 23. PIN: ADDR
Figure 26. PINS: REAEROUT, BASSO-L, BASSO-R
VS 20A
VS 20A
50K GND GND
GND
D95AU228A
D95AU230
Figure 24. PIN: REARIN
Figure 27. BASS-LI, BASS-RI, MIDDLE-L, MIDDLE-RII
VS
VS
20A
20A
SW
45K : Bass or 25K : MIDDLE
D95AU231A
50K GND Vref
D95AU229
GND BASS-LO
BASS-RO,MIDDLE-LO,MIDDLE-RO
18/23
TDA7430 - TDA7431
Figure 28. PIN: BASS-LO, BASS-RO, MIDDLELO, MIDDLE-RO, Figure 31. NBLIN, NBRIN
VS
VS
20A
20A
(*) GND BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI (*) 45K : Bass 25K : MIDDLE
D95AU232
GND
D95AU234
SW
Figure 32. NBLO, NBRO Figure 29. PIN:TREBLE-L, TREBLE-R,
VS 20A
VS
25K
VREF
GND
GND
D95AU235A
D95AU309
Figure 30. PIN VOUT REF,
VS 20A
GND
D95AU233A
10K GND
19/23
TDA7430 - TDA7431
Figure 33. TQFP44 (10 x 10) Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10 x 1.4mm)
0(min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B C L K
e
TQFP4410
0076922 D
20/23
TDA7430 - TDA7431
Figure 34. SDIP42 Mechanical Data & Package Dimensions
DIM. MIN. A A1 A2 B B1 c D E E1 e e1 e2 e3 L 2.54 0.51 3.05 0.38 0.89 0.23 36.58 15.24 12.70
mm TYP. MAX. 5.08 0.020 3.81 0.46 1.02 0.25 36.83 4.57 0.56 1.14 0.38 37.08 16.00 13.72 1.778 15.24 18.54 1.52 3.30 3.56 0.10 14.48 0.120 MIN.
inch TYP. MAX. 0.20
OUTLINE AND MECHANICAL DATA
0.150
0.180
0.0149 0.0181 0.0220 0.035 0.040 0.045
0.0090 0.0098 0.0150 1.440 0.60 0.50 0.540 0.070 0.60 0.730 0.060 0.130 0.140 1.450 1.460 0.629 0.570
SDIP42 (0.600")
E E1
A1
A2
B
B1
e
L
A
e1 e2
D c E 42 22
.015 0,38 Gage Plane
1
21
SDIP42
e3 e2
21/23
TDA7430 - TDA7431
Table 16. Revision History
Date January 2004 June 2004 Revision 9 10 Description of Changes First Issue in EDOCS DMS Changed the Style-sheet in compliance to the new "Corporate Technical Pubblications Design Guide"
22/23
TDA7430 - TDA7431
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
23/23

▲Up To Search▲

Price & Availability of TDA7430TR

	To Download TDA7430TR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .